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<citation_list><citation key="ref0"><unstructured_citation>B. Koenemann, &quot;LFSR-coded test patterns for scan designs,&quot; in Proc.Eur. Test Conf. (ETC), 1991, pp. 237-242.</unstructured_citation></citation><citation key="ref1"><unstructured_citation>V. Gherman, H. Wunderlich, H. Vranken, F. Hapke, M. Wittke, and M. Garbers, &quot;Efficient pattern mapping for deterministic logic BIST,&quot; in Proc. Int. Test Conf. (ITC), Oct. 2004, pp. 48-56.</unstructured_citation></citation><citation key="ref2"><doi>10.1109/VTS.2009.43</doi><unstructured_citation>A.-W. Hakmi, S. Holst, H. Wunderlich, J. Schloffel, F. Hapke, and A. Glowatz, &quot;Restrict encoding for mixed-mode BIST,&quot; in Proc. 27th IEEE VLSI Test Symp. (VTS), May 2009, pp. 179-184.</unstructured_citation></citation><citation key="ref3"><doi>10.1049/el:20083481</doi><unstructured_citation>A. S. Abu-Issa and S. F. Quigley, &quot;Bit-swapping LFSR for low-power BIST,&quot; Electron. Lett., vol. 44, no. 6, pp. 401-402, Mar. 2008.</unstructured_citation></citation><citation key="ref4"><doi>10.1109/TCAD.2004.826558</doi><unstructured_citation>J. Rajski, J. Tyszer, M. Kassab, and N. Mukherjee, &quot;Embedded deterministic test,&quot; IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 23, no. 5, pp. 776-792, May 2004.</unstructured_citation></citation><citation key="ref5"><unstructured_citation>S. Gerstendorfer and H. Wunderlich, &quot;Minimized power consumption for scan-based BIST,&quot; in Proc. Int. Test Conf. (ITC), 1999, pp. 77-84.</unstructured_citation></citation><citation key="ref6"><unstructured_citation>F. Corno, M. Rebaudengo, M. S. Reorda, G. Squillero, and M. Violante,&quot;Low power BIST via non-linear hybrid cellular automata,&quot; in Proc.18th IEEE Very Large Scale Integr. (VTSI) Test Symp., May 2000,pp. 29-34.</unstructured_citation></citation><citation key="ref7"><doi>10.1109/ATS.2010.67</doi><unstructured_citation>X. Lin and J. Rajski, &quot;Adaptive low shift power test pattern generator for logic BIST,&quot; in Proc. 19th IEEE Asian Test Symp. (ATS), Dec. 2010, pp. 355-360.</unstructured_citation></citation><citation key="ref8"><doi>10.1109/TCAD.2005.855927</doi><unstructured_citation>S. Wang and S. K. Gupta, &quot;LT-RTPG: A new test-per-scan BIST TPG for low switching activity,&quot; IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 25, no. 8, pp. 1565-1574, Aug. 2006.</unstructured_citation></citation><citation key="ref9"><doi>10.1109/TCAD.2002.1013896</doi><unstructured_citation>S. Wang and S. K. Gupta, &quot;DS-LFSR: A BIST TPG for low switching activity,&quot; IEEE Trans. Comput.-Aided Design Integr. Circuits Syst.,vol. 21, no. 7, pp. 842-851, Jul. 2002.</unstructured_citation></citation><citation key="ref10"><unstructured_citation>Michał Filipek, Grzegorz Mrugalski, Senior Member, IEEE, Nilanjan Mukherjee, Senior Member, IEEE, Benoit Nadeau-Dostie, Senior Member, IEEE, Janusz Rajski, Fellow, IEEE, Je˛drzej Solecki, and Jerzy Tyszer, Fellow, IEEE &quot;Low Power Programmable PRPG with Test compression capabilities&quot;.</unstructured_citation></citation><citation key="ref11"><doi>10.1109/VTS.2012.6231071</doi><unstructured_citation>J. Rajski, J. Tyszer, G. Mrugalski, and B. Nadeau-Dostie, &quot;Test generator with preselected toggling for low power built-in self-test,&quot; in Proc. IEEE 30th VLSI Test Symp. (VTS), Apr. 2012, pp. 1-6.</unstructured_citation></citation><citation key="ref12"><unstructured_citation>Janusz Rajski , Jerzy Tyszer, &quot; Design of phase shifter for BIST Applications&quot;.</unstructured_citation></citation><citation key="ref13"><unstructured_citation>X. Zhang and K. Roy, &quot;Power reduction in test-per-scan BIST,&quot; in Proc.6th IEEE Int. On-Line Test. Workshop (OLTW), Jul. 2000, pp. 133-138.</unstructured_citation></citation><citation key="ref14"><doi>10.1109/TEST.2006.297695</doi><unstructured_citation>C. Zoellin, H. Wunderlich, N. Maeding, and J. Leenstra, &quot;BIST power reduction using scan-chain disable in the cell processor,&quot; in Proc. Int.Test Conf. (ITC), Oct. 2006, pp. 1-8, paper 32.3.</unstructured_citation></citation><citation key="ref15"><unstructured_citation>P. Girard, L. Guiller, C. Landrault, and S. Pravossoudovitch, &quot;A test vector inhibiting technique for low energy BIST design.&quot;</unstructured_citation></citation></citation_list>
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