3d8d13581898e639443-4487 20230908005735487 beie:beie director@blueeyesintelligence.org WEB-FORM International Journal of Recent Technology and Engineering (IJRTE) IJRTE 22773878 10.35940/ijrte.2277-3878 https://www.ijrte.org/ 03 30 2019 7 6 Department of Electronics and Communication, Dayananda Sagar College of Engineering, Bengaluru (Karnataka), India. Krutthika H K https://orcid.org/0000-0003-0117-0856 Dr. Rajashekara Ph. D (IITB), Department of Electronics and Communication, Philips India Limited, Bengaluru (Karnataka), India. The increase in the applications for the innovative technologies has further increased the computing resources in a single chip. In such scenario, different application desires computing resources to build on a Single Chip. Therefore, interconnection between the IP cores becomes another challenging task. So, this led to the innovation of the Network on Chip as a novel platform those networks inside the System on Chip. There are many disadvantages of the traditional bus based architectures, as it blocks the traffic. The network topologies, routing algorithms and router architectures are the utmost critical part of any network structure. The execution of the system is measured by throughput. The throughput and effectiveness of interconnect depends on the system parameters. In this paper, we are reviewing the previous methods and approaches of routing algorithms and router architectures of NoC. 03 30 2019 1687 1691 CC BY-NC-ND 4.0 10.35940/BEIESP.CrossMarkPolicy www.ijrte.org true 10.35940/ijrte.F2131.037619 https://www.ijrte.org/portfolio-item/F2131037619/