<?xml version="1.0" encoding="UTF-8"?>
<doi_batch version="4.3.0" xmlns="http://www.crossref.org/doi_resources_schema/4.3.0" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.crossref.org/doi_resources_schema/4.3.0 http://www.crossref.org/schema/deposit/doi_resources4.3.0.xsd">
<head>
<doi_batch_id>b8d9ca7c-656f-4933-a07c-6328af877187</doi_batch_id>
<depositor>
<name>beie</name>
<email_address>director@blueeyesintelligence.org</email_address>
</depositor>
</head>
<body>
<doi_citations>
<doi>10.35940/ijrte.F2131.037619</doi>
<citation_list><citation key="ref0"><unstructured_citation>Sayed Mohsen Hashemi &quot;Performance Evaluation of Network-on-Chip Routing Deterministic and Adaptive Algorithms,&quot; International journal of Computer Science &amp; Network Solutions Feb.2015-Volume 3.No.2 http://www.ijcsns.com ISSN 2345-3397</unstructured_citation></citation><citation key="ref1"><unstructured_citation>Ville Rantala et al., &quot;Network on chip routing algorithms&quot;.</unstructured_citation></citation><citation key="ref2"><unstructured_citation>A. Adriahantenaina, H. Charlery, A. Greiner, L. Mortiez, C.A. Zeferino:&quot;SPIN: a Scalable, Packet Switched On-chip Micro-network&quot;, Design, Automation and Test in Europe Conference and Exhibition, 2003, p. 70-73.</unstructured_citation></citation><citation key="ref3"><unstructured_citation>Jian Wu, Zhen Zhang, and Chris Myers &quot;A Fault-Tolerant Routing Algorithm for a Network-on-Chip Using a Link Fault Model&quot;.</unstructured_citation></citation><citation key="ref4"><doi>10.1109/DSN.2006.35</doi><unstructured_citation>Dongkook Park, Chrysostomos Nicopoulos &quot;Exploring Fault-Tolerant Network-on-Chip Architectures*&quot;, Proceedings of the 2006 International Conference on Dependable Systems and Networks (DSN'06).</unstructured_citation></citation><citation key="ref5"><doi>10.1109/ISED.2012.68</doi><unstructured_citation>Prasun Ghosal et al., &quot;SD2D: A Novel Routing Architecture for Network-on-Chip&quot;, 2012 International Symposium on Electronic System Design (ISED).</unstructured_citation></citation><citation key="ref6"><unstructured_citation>E. Rijpkema, K. Goossens, P. Wielage: A Router Architecture for Networks on Silicon. Proceedings of Progress 2001, 2ndWorkshop on Embedded Systems.</unstructured_citation></citation><citation key="ref7"><doi>10.1109/MWSCAS.2005.1594428</doi><unstructured_citation>K. Oommen, D. Harle: &quot;Hardware Emulation of a Network on Chip Architecture Based on a Clockwork Routed Manhattan Street Network&quot;, International Conference on Field Programmable Logic and Applications, 24-26 August 2005, pages: 727-728.</unstructured_citation></citation><citation key="ref8"><doi>10.1145/1065579.1065726</doi><unstructured_citation>J. Kim, D. Park, T. Theocharides, N. Vijaykrishnan, C.R. Das: &quot;A Low Latency Router Supporting Adaptivity for On-Chip Interconnects:, Proceedings, 42. Design Automation Conference, 13-17 June 2005, pages: 559-564.</unstructured_citation></citation><citation key="ref9"><unstructured_citation>H. Kariniemi, J. Nurmi: &quot;Fault-tolerant XGFT Network-on-Chip for Multiprocessor System-on-Chip Circuits&quot;, International Conference on Field Programmable Logic and Applications, 24-26 August 2005, pages: 203-210.</unstructured_citation></citation><citation key="ref10"><doi>10.1016/j.camwa.2012.03.074</doi><unstructured_citation>Mostafa S. Sayed, Ahmed Shalaby, Mohamed El-Sayed, Victor Goulart: &quot;Flexible router architecture for network-on-chip&quot;, Computers and Mathematics with Applications 64 (2012) 1301-1310</unstructured_citation></citation><citation key="ref11"><doi>10.1109/GET.2015.7453784</doi><unstructured_citation>S.Shenbagavalli, S.Karthikeyan: &quot;An Efficient Low Power NoC Router Architecture Design&quot;, International Conference on Green Engineering and Technologies (IC-GET 2015).</unstructured_citation></citation><citation key="ref12"><unstructured_citation>Wan-Ting Su, Jih-Sheng Shen, Pao-Ann Hsiung: &quot;Network-on-Chip Router Design with Buffer-Stealing&quot;,16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011), INSPEC Accession Number: 11851913.</unstructured_citation></citation><citation key="ref13"><unstructured_citation>T. Bjerregaard, J. Sparso:&quot;A Router Architecture for Connection-Oriented Service Guarantees in the MANGO Clockless Network-on-Chip&quot;, Proceedings of the Design, Automation and Test in Europe Conference and Exhibition, 2005, Volume 2, pages: 1226-1231.</unstructured_citation></citation><citation key="ref14"><doi>10.1109/NORCHP.2005.1596991</doi><unstructured_citation>M. Ali, M. Welzl, S. Hellebrand:&quot;A Dynamic Routing Mechanism for Network on Chip&quot;,23rd NORCHIP Conference, 21-22 November 2005, pages: 70-73.</unstructured_citation></citation><citation key="ref15"><unstructured_citation>M. Alho, J. Nurmi: &quot;Implementation of interface router IP for Proteo network-on-chip&quot;,The 6th IEEE International Workshop on Design and Diagnostics of Electronics Circuits and Systems, Poznan, Poland, 2003.</unstructured_citation></citation><citation key="ref16"><unstructured_citation>L.Rooban, S.Dhananjeyan: &quot;Design of Router Architecture Based on Wormhole Switching Mode for NoC&quot;,International Journal of Scientific &amp; Engineering Research Volume 3, Issue 3, Marc h-2012 ISS N 2229-5518</unstructured_citation></citation><citation key="ref17"><doi>10.17485/ijst/2017/v10i38/115032</doi><unstructured_citation>Ajay Kumar et al., &quot;Extensible On-Chip Interconnect Architecture and Routing Methodology for NOC&quot;, Indian Journal of Science and Technology, Vol 10(38), DOI: 10.17485/ijst/2017/v10i38/115032, October 2017.</unstructured_citation></citation><citation key="ref18"><doi>10.1109/PRDC.2017.32</doi><unstructured_citation>Eberle A. Rambo et al.,&quot; Designing Networks-on-Chip for High Assurance Real-Time Systems&quot;,IEEE 22nd Pacific Rim International Symposium on Dependable Computing, 2017.</unstructured_citation></citation><citation key="ref19"><unstructured_citation>Tobias Bjerregaard and Jens Spars, &quot;A Router Architecture for Connection-Oriented Service Guarantees in the MANGO Clockless Network-on-Chip&quot;, Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE'05).</unstructured_citation></citation><citation key="ref20"><doi>10.5120/ijca2016909520</doi><unstructured_citation>Ruchika Chandravanshi et.,&quot; Network on Chip Router Architecture Performance Analysis by using VHDL&quot;, International Journal of Computer Applications (0975 - 8887) Volume 140 - No.13, April 2016.</unstructured_citation></citation><citation key="ref21"><unstructured_citation>Ali Ahmadinia et.,&quot; A Highly Adaptive and Efficient Router</unstructured_citation></citation><citation key="ref22"><unstructured_citation>Architecture for Network-on-Chip&quot;, Advance Access publication on January 10, 2011.</unstructured_citation></citation><citation key="ref23"><doi>10.1109/ICCUBEA.2016.7859989</doi><unstructured_citation>Ashish V Kayarkar et., &quot;Router Architecture for the Interconnection Network: A Review&quot;, 2016 International Conference on Computing Communication Control and automation (ICCUBEA).</unstructured_citation></citation><citation key="ref24"><unstructured_citation>Rohini, &quot;Design and Implementation of Minimal adaptive West first algorithm for NoC Router Architecture&quot;, Proceedings of National Conference on 'Women in Science &amp; Engineering' (NCWSE 2013), SDMCET Dharwad, ISSN 2277 - 4106</unstructured_citation></citation><citation key="ref25"><doi>10.1016/j.jcss.2012.09.007</doi><unstructured_citation>Chifeng Wang et., &quot;Scalable load balancing congestion-aware Network-on-Chip router architecture&quot; Journal of Computer and System Sciences, Volume 79, Issue 4, June 2013, Pages 421-439</unstructured_citation></citation></citation_list>
</doi_citations>
</body>
</doi_batch>
