396e3d57186c1f28fcb4b5c 20230720055431361 beie:beie director@blueeyesintelligence.org WEB-FORM International Journal of Recent Technology and Engineering (IJRTE) IJRTE 22773878 10.35940/ijrte.2277-3878 https://www.ijrte.org/ 07 30 2023 12 2 Professor, Department of Electronics and Communications Engineering, Vignana Bharathi Institute of Technology, Hyderabad (Telangana), India. Dr. Sharmila Vallem https://orcid.org/0000-0001-5312-1066 G. Tejaswi https://orcid.org/0009-0008-4402-0659 Students, Department of Electronics and Communication Engineering, Vignana Bharathi Institute of Technology, Hyderabad. (Telangana), India. Hrithik Sidharth https://orcid.org/0009-0002-8876-2351 Students, Department of Electronics and Communication Engineering, Vignana Bharathi Institute of Technology, Hyderabad. (Telangana), India. Shilpa Reddy https://orcid.org/0009-0004-2318-3310 Students, Department of Electronics and Communication Engineering, Vignana Bharathi Institute of Technology, Hyderabad. (Telangana), India. An area-efficient high Wallace tree multiplier using adders is presented in this paper. The proposed Wallace tree multiplier is designed using logic gates and adders. The design is implemented in Cadence Virtuoso using a 45-nm technology library. The proposed design offers reduced delay and higher performance than conventional multipliers using carry-save adders with majority-based gate adder logic. The design also offers a reduced transistor count of 12, which is minimal compared to that of the conventional design. One of the fundamental building blocks of many VLSI applications is multipliers. To enhance the performance of circuits and systems, the design of multipliers is very important. The key feature of a high-performance Wallace tree multiplier lies in its efficient reduction of partial product additions. By utilising a combination of carry-save and carry-propagate adders, it minimises the critical path delay and maximises the speed of multiplication. Additionally, advanced optimisation techniques such as parallel prefix adders and parallel carry-save adders can be employed to further improve performance. 07 30 2023 20 25 CC BY-NC-ND 4.0 10.35940/BEIESP.CrossMarkPolicy www.ijrte.org true International Journal of Recent Technology and Engineering (IJRTE) No, We did not receive. No conflicts of interest to the best of our knowledge. No, the article does not require ethical approval and consent to participate with evidence. Not relevant All authors having equal contribution for this article. 10.35940/ijrte.B7685.0712223 https://www.ijrte.org/portfolio-item/B76850712223/