-1e416013186c20a17cb-67bc 20230325062018534 beie:beie director@blueeyesintelligence.org WEB-FORM International Journal of Recent Technology and Engineering (IJRTE) IJRTE 22773878 10.35940/ijrte.2277-3878 https://www.ijrte.org/ 03 30 2023 11 6 Department of Computer Science, Dev Sanskriti Vishwavidyalaya, Haridwar (Uttarakhand), India Dr. Chandrashekhar Patel https://orcid.org/0000-0003-0379-673X Prof. Abhay Saxena https://orcid.org/0000-0001-7685-7607 Dean, School of Technology, Management & Communication, Dev Sanskriti Vishwaviidyalya, Hardwar (Uttarakhand), India. Prof. (Dr.) Anita Rawat Director, Uttarakhand Science Education and Research Centre (USERC), Dehradun (Uttarakhand), India. Prof. Omprakash Nautiyal Uttarakhand Science Education & Research Centre (USERC) Dehradun (Uttarakhand), India. Objectives: The 4-bit ALU of a RISC processor is designed as shown by the researcher in this paper. The 4-bit ALU used in this work can perform 24 = 16 various arithmetic and logical operations, including addition, subtraction, multiplication, and division as well as logical AND, OR, NAND, NOR, NOT, XOR, XNOR, INCREMENT, DECREMENT, ROTATE LEFT, and ROTATE RIGHT. Methods: The author used the Vivado simulation tools with the Verilog HDL language to build the FPGA-based ALU, and the SP701 Spartan FPGA board was used to implement the entire design. It has been implemented to use energy-efficient IO standard approaches. Findings: By calculating the overall power usage at the pre- and post-levels, this research has developed a new method for building energy-efficient FPGA-based ALUs. Author utilized Vivado simulation tool for this investigation. The SP701 FPGA board has also been used to implement this idea. Novelty: The Internet of Things and other emerging digital era technologies will undoubtedly benefit from this research work, and its energy efficient design will support environmental initiatives. 03 30 2023 102 110 CC BY-NC-ND 4.0 10.35940/BEIESP.CrossMarkPolicy www.ijrte.org true No, we did not receive. No conflicts of interest to the best of our knowledge. No, the article does not require ethical approval and consent to participate with evidence. Data Collection: Vivado Software Implementation tool: SP701 Board. Dr. Chandrashekhar Patel: Implementation with SP701 Board, Prof. Abhay Saxena: Idea Generation, Dr. Anita Rawat: Framing the whole idea in conceptual manner Dr. Om Prakash Nautiyal: Analysis of the whole collected data. 10.35940/ijrte.F7498.0311623 https://www.ijrte.org/portfolio-item/F74980311623/