9c6b75ff-9fa4-4485-95fb-bcad821c9937 beie director@blueeyesintelligence.org 10.35940/ijrte.F7498.0311623 10.21058/gjecs.2016.11004S.Pandey G.Verma B. Das T.Kumar M.Dhankar "Energy Efficient Solar Charge Sensor Design Using Spartan-6 FPGA "Gyancity Journal of Electronics and Computer Science, Vol.1, No.1, pp.18-24, September 2016 ISSN: 2446-2918 DOI: 10.21058/gjecs.2016.11004. [CrossRef]10.17485/ijst/2016/v9i46/106916A Saxena, A Bhatt, P Gautam, P Verma, C Patel,"High Performance FIFO Design for Processor through Voltage Scaling Technique" In Indian Journal of Science and Technology Vol 9(45), DOI: 10.17485/ijst/2016/v9i45/106916, December 2016. [CrossRef]Swiegers, W., Johan H.R. Enslin, 1998. An Integrated Maximum Power Point Tracker for Photovoltaic Panels. [Online], Available: IEEE Explore database. [20th July 2006].10.1049/ip-gtd:19951577Hussein, K.H, I. Muta, T. Hoshino and M. Osakada, 2006. Maximum Photovoltaic Power Tracking: an algorithm for rapidly changing atmospheric conditions. [Online], IEEE Proceeding of Generation, Transmission and Distribution, pp: 142. [CrossRef]10.14445/22312803/IJCTT-V42P112A Saxena, S Gaidhani, A Pant, C Patel "Capacitance Scaling Based Low Power Comparator Design on 28nm FPGA" in International Journal of Computer Trends and Technology (IJCTT) - Volume X Issue Y- Month 2015 [CrossRef]10.17485/ijst/2017/v10i4/110890A Saxena, C Patel, M.Khan "Energy Efficient CRC Design for Processor ofWorkstation, and Server using LVCMOS " in Indian Journal of Science and Technology, Vol 10(4), DOI: 10.17485/ijst/2017/v10i4/110890, January 2017. [CrossRef]10.1109/IICPE.2014.7115800A.Singla,A.Kaur, B.Pandey "LVCMOS based energy efficient solar charge sensor design on FPGA" in Power Electronics (IICPE), 2014 IEEE 6th India International Conference DOI: 10.1109/IICPE.2014.7115800. [CrossRef]M. Renovell, J. Figueras, Y. Zorian, "Test of RAM-Based FPGA: Methodology and Application to the Interconnect", 15th IEEE VLSITest Symposium, pp. 230-237, 1997, Monterey, CA. [CrossRef]10.18489/sacj.v56i1.252R Roux, G. Schoor,P. Vuuren" Block RAM-based architecture for realtime reconfiguration using Xilinx R FPGAs" Research Article -SACJ 56, July 2015. [CrossRef]10.21058/gjet.2017.31006C.Patel, P.Verma, P. Agarwal, A.Omer,B. Gururani, S.Verma "Designing Green ECG Machine Basedon Artix-7 28nm FPGA " Gyancity Journal of Engineering and Technology,Vol.3, No.1, pp. 36-41, January 2017ISSN: 2456-0065 DOI:10.21058/gjet.2017.31006 [CrossRef]W.K. Huang and F. Lombardi, "An Approach for Testing Programmable/Configurable Field Programmable Gate Arrays,14th IEEE VLSI Test Symposium, pp. 450-455, Princeton, NJ,USA, May 1996.10.21817/ijet/2017/v9i2/170902113A Saxena, S Sharma, P Agarwal, C Patel "SSTL Based Energy Efficient FIFO Design for High Performance Processor of Portable Devices" in International Journal of Engineering and Technology (IJET)Vol 9 No 2 Apr-May 2017DOI: 10.21817/ijet/2017/v9i2/170902113. [CrossRef]