Design of Area and Power Efficient Multiplier Unit using Wallace Tree Algorithm
R.Krishnaveni1, P.Sakthy Priya2, B.Sivaranjani3, M.Sathish Kumar M.E.4, I.Vivek Anand M.E.5
1R.Krishnaveni, Electronics and Communication Department, National Engineering College, Kovilpatti, India.
2P.Sakthy Priya, Electronics and Communication Department, National Engineering College, Kovilpatti, India.
3B.Sivaranjani, Electronics and Communication Department, National Engineering College, Kovilpatti, India.
4M.Sathish Kumar M.E., Assistant Professor, Electronics and Communication Department, National Engineering College, Kovilpatti, India.
5I.Vivek Anand M.E., Assistant Professor, Electronics and Communication Department, National Engineering College, Kovilpatti, India.
Manuscript received on April 02, 2020. | Revised Manuscript received on April 21, 2020. | Manuscript published on May 30, 2020. | PP: 1350-1354 | Volume-9 Issue-1, May 2020. | Retrieval Number: F9509038620/2020©BEIESP | DOI: 10.35940/ijrte.F9509.059120
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: In any processing system, the core data path element may be a multiplier that particularly associated with DSP applications, which concludes overall processing unit performance. In such system, the multiplier unit improves the performance will boost up the potential. The Cadence EDA performs for high-speed multiplier evaluation consisting 64 x 64 bit in ASIC Digital flow (RTL-GDSII). Using carry select adder and carry save adder, the proposed multiplier intend with Wallace structure for enhancing the speed criteria. Wallace rebate absorbs more time for designing because it is more complex and aberrant in format for better width. Real Time signal processor requires high productive capacity and fewer reaction time. A classic scheme could be today in IOT utilizations. The proposed method concentrates on designing low power and area efficient in digital flow using the Wallace tree algorithm. The 180 nm CMOS technology for pursuance and outcome are related with other existing methods in delay, area and dynamic power dissipation.
Keywords: ASIC Digital flow, Cadence EDA, Carry select adder, Wallace tree structure.
Scope of the Article: Behaviour of Structures