Performance Assessment of RISC-V Architecture
Lakshamaiah Alluri1, Bhaskar M2, Hemant Jeevan Magadum3
1Lakshmaiah Alluri*, HDG, CDAC, Thiruvananthapuram, India.
2Dr. M Bhaskar, Professor, Department of Electronics and Communication, NIT, Trichy, India.
3Hemant Jeevan Magadum, ITNS, CDAC, Thiruvananthapuram, India.
Manuscript received on March 15, 2020. | Revised Manuscript received on March 24, 2020. | Manuscript published on March 30, 2020. | PP: 4576-4581 | Volume-8 Issue-6, March 2020. | Retrieval Number: F9352038620/2020©BEIESP | DOI: 10.35940/ijrte.F9352.038620
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: This paper presents the performance evaluation of RISC – V architecture based processor using Gem5 simulator. The performance analysis metrics such as bandwidth, latency, throughput, branch prediction, pipeline stages and memory hierarchy of the processor architecture are studied using Gem5 simulator. Different simulation models are carried out to arrive the best reference model for RISC-V architecture design and development. In this reference model cache memory functionality feature is verified with the verification methodology called Universal Verification Methodology (UVM). From simulations it is found that both the program and data cache provides optimum performance in terms of execution time, hit rates, miss rate and miss latencies.
Keywords: RISC-V, Gem5, UVM, Evaluation, System C, Openvera.
Scope of the Article: Network Architectures.