Memory Arbitration in DDR3
S. V. Vijayalakshmi1, A. Apsara2, K. Preetha3, S. Cammillus4
1S. V. Vijayalakshmi, Department of Electronics and Communication Engineering at National Engineering College , Tamil Nadu, India.
2A. Apsara, Department of Electronics and Communication Engineering at National Engineering College , Tamil Nadu, India.
3K. Preetha, Department of Electronics and Communication Engineering at National Engineering College , Tamil Nadu, India.
4S. Cammillus, Assistant professor, Department of Electronics and Communication Engineering at National Engineering College , Tamil Nadu, India.
Manuscript received on March 12, 2020. | Revised Manuscript received on March 25, 2020. | Manuscript published on March 30, 2020. | PP: 3344-3347 | Volume-8 Issue-6, March 2020. | Retrieval Number: F8524038620/2020©BEIESP | DOI: 10.35940/ijrte.F8701.038620
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Modern applications need expeditious, speed parallel processing elements with desired output within the stipulated time. As sundry applications increase demands expeditious processing, low power consumption, truncated deadlock of recollection. Hence, memory deadlock, memory starvation, and allocation of memory for genuine-time applications are the real challenges of the desired real world. The work fixates on abbreviated power consumption, deadlock for the inputs onto the output. DVFS (Dynamic Voltage and Frequency Shifting) and Co C (Cloud of chips) are acclimated to abbreviate the deadlock and to utilize the recollection efficaciously for input onto output. The results show the potency consumption as truncated compared to the antecedent results.
Keywords: Arbitration, Deadlock, Memory Starvation, Multi Processor System on Chip
Scope of the Article: Multi-Agent Systems.