Design of Modified Reconfigurable Unsymmetrical Six Parallel FIR Filter with Retiming Technique for Low Power & High-Speed Applications
P. Radhika1, T. Vigneswaran2, J. Selvakumar3
1P. Radhika, Asst. Prof, Department of Engineering and Communication Engineering, SRMIST, Chennai, Kattankulathur-603203, India.
2T. Vigneswaran, Prof, Department of Engineering and Communication Engineering, VIT Chennai, India
3J. Sselvakumar, Associate Prof, SRMIST, Chennai, India
Manuscript received on 20 April 2019 | Revised Manuscript received on 26 May 2019 | Manuscript published on 30 May 2019 | PP: 759-767 | Volume-8 Issue-1, May 2019 | Retrieval Number: F2820037619/19©BEIESP
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Abstract: Currently, filters with larger length are being widely used in several applications. Hence parallel processing is needed for digital signal processing (DSP) applications. Parallel reconfigurable FIR filter is mainly used for several applications such as SDR, multi standard video codec, digital communication system and wireless communication etc. Fast Fourier algorithm (FFA) technique is used to design the parallel FIR filter to reduce the complexity of the filter structure. The ordinary six parallel FIR filter without FFA and with Wallace multiplier is designed in the conventional technique. It needs more number of adders and multiplier to perform six parallel FIR filter. Hence the area and power is high in the existing filter. FFA technique is applied in the proposed six parallel FIR filter to reduce the number of adder and multiplier by simplifying the existing filter equations. Also the compact booth multiplier structure is applied in the proposed filter instead of Wallace multiplier. Hence it is called as Modified Reconfigurable unsymmetrical six parallel FIR filter (MRUSPF). The MRUSPF structure is presented in this paper to reduce the number of adders, register, half adder and full adder by clustering the filter coefficients. The number of gates and transistors are reduced by using logical and circuit level reduction method based on Boolean logic. Also sum of the coefficients are reused. Combinations of 2X2 FFA and 3X3 FFA structures are used to form the reconfigurable unsymmetrical six parallel. Also retiming technique is applied in reduced carry select adder, booth multiplier and proposed six parallel FIR filter to reduce the number of registers and switching activity of the clock. Retiming is nothing but changing the position of delay element such as flip-flop in order to achieve low area and low power. Simulation and synthesis processes are carried out by analog and digital Cadence virtuoso tools with 90nm CMOS technology. From the obtained results, it is concluded that, the proposed reconfigurable unsymmetrical six parallel FIR filter with retiming technique provides 28.3% power reduction and 50.3% delay reduction than the conventional proposed six parallel FIR filter without retiming structure.
Index Terms: Reconfigurable Unsymmetrical Six Parallel FIR Filter, Retiming Technique, FFA Technique, Wallace Multiplier, Booth Multiplier and Reduced Carry Select Adder.
Scope of the Article: Reconfigurable Computing