Area and Interconnect Length Optimization for VLSI Floor Planning Problem By using Harmony Search Algorithm
S. Venkatraman1, M. Sundhararajan2
1S. Venkatraman, Research Scholar, Department of Electronics and Communication Engineering, Bharath University, Chennai (Tamil Nadu), India.
2M. Sundhararajan, Dean Research, Department of Electronics and Communication Engineering, Bharath University, Chennai (Tamil Nadu), India.
Manuscript received on 23 April 2019 | Revised Manuscript received on 02 May 2019 | Manuscript Published on 07 May 2019 | PP: 139-143 | Volume-7 Issue-6S3 April 2019 | Retrieval Number: F1027376S19/2019©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Floor planning is that the terribly central stage in VLSI physical style for class conscious building module style methodology. Floor planning affords early response that evaluates architectural choices, approximation of chip space, estimates delay; interconnect length and congestion caused by wiring. As technology advances, style complexness is increasing and therefore the circuit size is obtaining larger. Thus space of the circuit gets increase and tougher to minimizing the interconnect length. The VLSI floor planning is that the NP onerous downside. So it’s horribly troublesome to seek out the best solution. During this paper we tend to take into account, a multi-objective hybrid genetic algorithmic program primarily based floor planning has been developed with novel crossover operators to handle the multi-objective floor planning for Very Large Scale Integration application specific integrated circuits (VLSI ASICs). The Genetic algorithmic program (GA) with harmony search algorithm approach is employed for minimizing the whole space and interconnects length.
Keywords: VLSI Slicing Floorplan, Harmony Search Algorithm (HAS), Area and Wirelength.
Scope of the Article: VLSI Algorithms