Arithmetic and Logic Unit Designing Using Reversible Logic Gate
Divyansh Mathur1, Arti Saxena2, Abneesh Saxena3
1Divyansh Mathur, Student IVth Year, Department of Electronics and Communication, PSIT-COE, Kanpur (U.P.), India.
2Arti Saxena, Head of Department, Department of Electronics and Communication, PSIT-COE, Kanpur (U.P.), India.
3Abneesh Saxena, Department of JWM, Ordnance Factory, Kanpur (U.P.), India.
Manuscript received on 21 January 2013 | Revised Manuscript received on 28 January 2013 | Manuscript published on 30 January 2013 | PP: 157-160 | Volume-1 Issue-6, January 2013 | Retrieval Number: F0423021613/2013©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Owing to its unique technique of One-to-One Mapping between the inputs and the corresponding outputs, the ReversibleLogicGates are now finding profound as well as promising applications in emerging growing paradigms such as Quantum Computing, Quantum Dot Cellular Automata, Optical Computing, Digital Signal Processing, Low Power CMOS Design, Nanotechnology etc. The Reversible Logic has received great attention in the past recent years due to its ability in reducing the power dissipation, the major concern in digital designing. To generate a useful gate function the Reversible Gates require constant inputs, called Ancillary Inputs, and some additional unused outputs, called Garbage Outputs, in order to maintain the reversibility of the digital circuits. The paper presents a novel design of different Arithmetic and Logic Units such as Half Adder, Half Subtracter and 1-Bit Comparator, using the existing Reversible Gates and the proposed new Reversible CNOT, BJN, and Peres Gates.
Keywords: CNOT Gate, Peres Gate, BJN Gate.
Scope of the Article: Fuzzy Logics