Performance Optimization of Logic Circuits based on Hybrid CMOS and CNFET Design
Shimaa I. Sayed1, M.M.Abutaleb2, Zaki B. Nossair3
1Eng. Shimaa I. Sayed, Department of Communication and Electronics, Helwan University, Faculty of Engineering, Cairo, Egypt.
2Dr. M.M. Abutaleb, Department of Communication and Electronics, Helwan University, Faculty of Engineering, Cairo, Egypt.
3Prof. Zaki B. Nossair, Department of Communication and Electronics, Helwan University, Faculty of Engineering, Cairo, Egypt.
Manuscript received on 21 January 2013 | Revised Manuscript received on 28 January 2013 | Manuscript published on 30 January 2013 | PP: 1-3333 | Volume-1 Issue-6, January 2013 | Retrieval Number: F0378021613/2013©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: There is a pressing need to explore circuit design ideas in new emerging technologies in deep-submicron in order to exploit their full potential during the early stages of their development. Carbon nanotube (CNT) based technology has significant potential to replace silicon technology sometimes in the future. Single-walled carbon nanotubes are investigated for applications in logic and sensing circuits due to their superior transport properties. CMOS (complementary metal oxide semiconductor) technology is better in switching speed specially for NMOS. In this work we take advantage of the high mobility transport in p-type CNTFETs and combine them with high-performance conventional n-type MOSFETs, thereby achieving the best overall performance in a hybrid configuration. This paper presents a detailed simulation based assessment of circuit performance of this technology and compares it with 32nm CMOS and 32nm CNFET technologies. It is shown that the performance of the hybrid PCNFET-NMOS configuration is better than that of the pure CMOS in terms of noise margin (32.8% higher) and power consumption (60% lower) and therefore (2.5% lower )in PDP. The performance of PCNFET-NMOS is the same of pure CNFET for noise margin, 65% lower in power consumption and 2% lower in PDP. Also this integration of a carbon nanotube on an underlying CMOS circuit achieves a large saving in area that is amenable to future nanoscale device integration.
Keywords: CNFET, CMOS Technology, Hybrid Design, Noise Margin, Power Delay Product.
Scope of the Article: Discrete Optimization