High Speed PS0 Micro-Pipelined Adder
Mansi Jhamb1, Hinduja Pudi2, Sukant Vats3
1Mansi Jhamb, Assistant Professor, University School of Information Communication and Technology, GGSIPU, New Delhi, India
2Hinduja Pudi*, University School of Information Communication and Technology, GGSIPU, New Delhi, India.
3Sukant Vats, University School of Information Communication and Technology, GGSIPU, New Delhi, India.
Manuscript received on January 05, 2020. | Revised Manuscript received on January 25, 2020. | Manuscript published on January 30, 2020. | PP: 4066-4072 | Volume-8 Issue-5, January 2020. | Retrieval Number: E6655018520/2020©BEIESP | DOI: 10.35940/ijrte.E6655.018520
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: For continuous monitoring of individual wellbeing, wearable devices are indispensable. The limitations of cost, utilization of power, delay and restricted device measurements are the basic issues which should be dealt cautiously while designing these battery powered devices. The wearables use high-end processors dedicated for complicated signal processing. Data path plays a key role in every digital signal processor. Adder is the most widely used component in wearable technology. This work proposes a novel architecture for PS0 pipelined adder. The proposed adder is implemented in 65nm TSMC CMOS and its performance has been compared with state-of-art adders. The SPICE level simulations are performed on HSPICE using 65nm TSMC CMOS @ 1.2 V. All the designs have been simulated with extracted wire and layout parasitics. The proposed adder ensures the lowest propagation delay which is 79.33% less when compared to RCA and has a power dissipation of 0.225 mw which is 25.4 % less as compared to CLA. Besides, the proposed adder offers a benefit of having lower transistor count which is 49.6% less as compared to RCA.
Keywords: Adder, Pipeline, Asynchronous, Completion Detector Circuit (CDC), Ripple Carry Adder (RCA), Carry Select Adder (CSA), Carry Lookahead Adder (CLA).
Scope of the Article: High Speed Networks.