Logical Fault Modelling Algorithm for Stuck-at-fault
K. Mariya Priyadarshini1, Vipul Agarwal2, R. S Ernest Ravindran3, K. Mercy Romitha4, Pritika Kanchan5, Kurra Harshita6
1K. Mariya Priyadarshini, Department of Electronics and Communication Engineering, Koneru Lakshmaiah Education Foundation, Vaddeswaram, AP, India.
2Vipul Agarwal, Department of Electronics and Communication Engineering, Koneru Lakshmaiah Education Foundation, Vaddeswaram, AP, India.
3R.S Ernest Ravindran, Department of Electronics and Communication Engineering, Koneru Lakshmaiah Education Foundation, Vaddeswaram, AP, India.
4K. Mercy Romitha, Department of Electronics and Communication Engineering, Koneru Lakshmaiah Education Foundation, Vaddeswaram, AP, India.
5Pritika Kanchan, Department of Electronics and Communication Engineering, Koneru Lakshmaiah Education Foundation, Vaddeswaram, AP, India.
6Kurra Harshita, Department of Electronics and Communication Engineering, Koneru Lakshmaiah Education Foundation, Vaddeswaram, AP, India.
Manuscript received on January 05, 2020. | Revised Manuscript received on January 25, 2020. | Manuscript published on January 30, 2020. | PP: 4302-4306 | Volume-8 Issue-5, January 2020. | Retrieval Number: E4955018520/2020©BEIESP | DOI: 10.35940/ijrte.E4955.018520
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: With miniaturization happening around with the technology, it’s very important that the faults associated with these circuitsto get accurate results, especially electronics circuits. Besides, finding these faults is a tough job as there will be several test inputs that needs to be tested to check the circuit is fault free or not. Stuck at line is a deficiency prototype used as a part of computerized testing circuit. When any of the line in the circuit is stuck permanently at power supply or ground giving unwanted output, this is called fault. This paper describes about a technique that can be used to find stuck at fault and display the test vectors that generates the faulty output.Any self-assertive different shortcoming in combinational and consecutive circuits can be mimicked and tried utilizing the displayed stuck at fault model. High fault coverage is especially significant during assembling test, and strategies. Stuck at fault results are presented and detected. The outcomes of single stuck at faults are presented in this paper using Verilog code.
Keywords: Fault Algorithm, Stuck-at-fault, Single Stuck-at-fault, Test Pattern Generation
Scope of the Article: Parallel and Distributed Algorithms.