Implementation of 64-Bits Radix – 8 IFFT for Computation Speed by IDIF using Verilog
B. Anil Kumar1, M. Naveen Reddy2, Vamshi Kollipara3, B. Rajesh4
1B. Anil Kumar, Assistant Professor,Dept of ECE,Malla Reddy Institute Of Engineering And Technology,Hyd.,TS, India.
2M.Naveen Reddy, B.Tech Student, Dept of ECE, Malla Reddy Institute Of Engineering And Technology, Hyd., TS, India.
3VamshiKollipara, Assistant Professor,Dept of ECE,Malla Reddy Institute Of Engineering And Technology,Hyd.,TS, India.
4B.Rajesh, Student, B.Tech Student, Dept of ECE, Malla Reddy Institute Of Engineering And Technology, Hyd., TS, India.
Manuscript received on January 05, 2020. | Revised Manuscript received on January 25, 2020. | Manuscript published on January 30, 2020. | PP: 5274-5279 | Volume-8 Issue-5, January 2020. | Retrieval Number: E3209018520/2020©BEIESP | DOI: 10.35940/ijrte.E3209.018520
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Always technical designers choice includes algorithms, flowcharts, programming etc and the end users requires given input and application output. Based upon this view this paper focus on the advancement of Inverse Fast Fourier Transform(IFFT) by doing design and observing the performance analysis of 64 point IFFT, using Radix-8 algorithm. The algorithm is developed by Inverse Decimation In Frequency(IDIF) of IFFT, using Verilog as design entity and synthesis are performed in Xilinx. In this architecture the numbers of stages are reduced to 75%.
Keywords: IFFT, IDIF, Verilog, XILINX.
Scope of the Article: Exact and Parameterized Computation.