Loading

Anti-Windup PI Controller with Tracking for BLDC Motor Drive System: Modeling, Simulation and Implementation on Lab View Based FPGA
B. Gunapriya1, M. Karthik2, I. Abinaya3, R. R. Rubia Gandhi4, H. Vidhya5
1Dr. B. Gunapriya, Department of EEE, New Horizon College of Engineering, Bengaluru, Karnataka, India.
2M. Karthik, Department of EEE, Sri Ramakrishna Engineering College, Coimbatore, India.
3I. Abinaya, Department of EEE, Sri Ramakrishna Engineering College, Coimbatore, India.
4R. R. Rubia Gandhi, Department of EEE, Sri Ramakrishna Engineering College, Coimbatore, India.
5H.Vidhya, Department of EEE, Sri Krishna College of Engineering & Technology, Coimbatore, India. 

Manuscript received on January 02, 2020. | Revised Manuscript received on January 15, 2020. | Manuscript published on January 30, 2020. | PP: 2064-2070 | Volume-8 Issue-5, January 2020. | Retrieval Number: D9510118419/2020©BEIESP | DOI: 10.35940/ijrte.D9510.018520

Open Access | Ethics and Policies | Cite | Mendeley
© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: Most of the Brushless DC (BLDC) motors drives take up proportional integral (PI) controller and pulse width modulation (PWM) scheme for speed control. BLDC motor drive has strong saturation characteristics and saturation results in a windup phenomenon. This paper presents an Anti-windup drive for BLDC motor. An Anti-windup controller (AWC) with tracking has been employed and which has been modeled in MATLAB / Simulink and comparison has been done between conventional PI controller and AWC with tracking at different starting loads. In this paper, dynamic characteristics of the BLDC motor drive have been examined and results are validated with FPGA (Field Programmable Gate Array) based experimental set up.
Keywords: BLDC, Anti-windup, PI, FPGA.
Scope of the Article: FPGAs.