Design and Simulation of Error Amplifier used in Power Management chips
KM Sudharshan1, BP Divakar2
1KM Sudharshan*, School of ECE, REVA University, Bangalore, India.
2BP Divakar, School of EEE, REVA University, Bangalore, India.
Manuscript received on November 15, 2019. | Revised Manuscript received on November 23, 2019. | Manuscript published on November 30, 2019. | PP: 2123-2127 | Volume-8 Issue-4, November 2019. | Retrieval Number: D7703118419/2019©BEIESP | DOI: 10.35940/ijrte.D7703.118419
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: This paper discusses the design procedure of error amplifier, which is used in the power factor correction circuit built with dc-dc Boost converter. The error amplifier is the heart of the power management IC’s which indicates the accuracy of the entire circuitry. The specifications are considered which is suitable for power management applications. The gain of the amplifier is chosen to be 60db, UGB of 75MHz, slew rate of 50V/uS, PM greater than 60’, technology 180nm. The design is simulated using tsmc 180nm technology with Analog Device’s LT-SPICE simulator.
Keywords: CMOS Opamp, Error Amplifier.
Scope of the Article: Data Management.