Implementation of Double Tail Dynamic Latched Architecture for High Speed ADC
M.Swarna Lakshmi1, Allabaksh Shaik2, V.Nagendra Kumar3, K.Lokesh Krishna4
1M.Swarna Lakshmi, Department of ECE, S. V. College of Engineering, Tirupati, Andhra Pradesh, India.
2Allabaksh Shaik, Department of ECE, S. V. College of Engineering, Tirupati, Andhra Pradesh, India.
3V.Nagendra Kumar, Department of ECE, S. V. College of Engineering, Tirupati, Andhra Pradesh, India.
4K. Lokesh Krishna, Department of ECE, S. V. College of Engineering, Tirupati, Andhra Pradesh, India.
Manuscript received on 15 August 2019. | Revised Manuscript received on 24 August 2019. | Manuscript published on 30 September 2019. | PP: 5966-5970 | Volume-8 Issue-3 September 2019 | Retrieval Number: C6263098319/19©BEIESP | DOI: 10.35940/ijrte.C6263.098319
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: In this proposed work, a low offset voltage (mV) and high speed voltage comparator circuit is designed and simulated. With the unceasing rise of various wireless portable communication systems, high speed transceiver circuits, and high speed memory circuit design, sensitized sensor technologies, and wireless sensor network design, the design of high speed, low offset voltage and low power operated comparators are indispensable blocks in the design of a very good analog to digital converter architecture. The proposed work does not entail the usage of any pre-amplification stages, which accounts for the direct reduction of current consumption and silicon area. The MOSFETs at the input differential pair stage of the CMOS comparator circuit are designed to operate in near sub-threshold region rather than in saturation region to account for the low power consumption. The proposed double tail dynamic latched comparator in this work is implemented in 90μm CMOS technology with the operating power supply voltage (VDD) of 1.2 V and sampling frequency of 600 MHz using Microwind EDA tool. The simulated results indicate that the total power consumption is calculated to be of the order of 126.3μw with the delay of 876ps. From the obtained results, the proposed double tail dynamic latched circuit has considerably lowered both the propagation delay time and power consumption, when compared to the previous works.
Keywords: Low offset, Low Power, Gain Stages Latch and Pre-Amplifier.
Scope of the Article: Network Architectures