Effective Analysis of an Iterative Median Filter-Hardware and Software Perspective
Archana H R1, C R Byra Reddy2, Narendra C P3
1Archana H R *, Department of ECE, BMSCE , Bangalore.
2Dr C R Byra Reddy, Department of ECE , BIT, Bangalore.
3Dr Narendra C P, department, Name of the affiliated College or University/Industry, City, Country.
Manuscript received on 11 August 2019. | Revised Manuscript received on 14 August 2019. | Manuscript published on 30 September 2019. | PP: 5580-5583 | Volume-8 Issue-3 September 2019 | Retrieval Number: C5564098319/2019©BEIESP | DOI: 10.35940/ijrte.C5564.098319
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Image quality enhancement is a very predominant domain of discussion as the complexity of system increases, the software implementation becomes a key factor but it is not always reliable to use the approach for adaptable applications such as medical, military or real time purpose. In order to address such scenarios it is necessary to have a reconfigurable and an adaptable implementation. In this paper we have addressed the hardware modeling of a median filter using double iteration process. The iterative median filter is implemented on an Artix-7 FPGA.
Keywords: Median Filter, FPGA, Sorter, Error Detection, PSNR, Noise
Scope of the Article: Image analysis and Processing