Low Cost Hardware Architecture of Fast Lifting Wavelet Transform for Image Compression
K.Ezhilarasan1, D.Jayadevappa2, Pushpa Mala S3
1K Ezhilarasan*, Research Scholar, Jain University, Karnataka, India.
2D Jayadevappa, Electronics and Instrumentation Engg. JSS Academy of Technical Education, Karnataka, India.
3Pushpamala S, Electronics and Communication, Dayanand Sagar University, Karnataka, India.
Manuscript received on 01 August 2019. | Revised Manuscript received on 09 August 2019. | Manuscript published on 30 September 2019. | PP: 6504-6514 | Volume-8 Issue-3 September 2019 | Retrieval Number: C5018098319/2019©BEIESP | DOI: 10.35940/ijrte.C5018.098319
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: In this work, the researchers have given a low-cost, multiplier-less design with latest DWT (2D lifting technology) for high-speed dual-Z scans. A single dimension parallele row, column processors and five transposing registers are the suggested architecture. Furthermore, a 4N timeline buffer is used to process 2D DWT images with NxN resolution. Flipping architecture is intended to decrease the critical path, replacing multipliers with shifting and adding logic. To reduce transposition and latency buffers, dual Z scanning technology is introduced. The proposed architecture is better for similar performance requirements than the existing hardware architectures. Verilog is defined as the suggested Design Register Transfer Logic (RTL) and is synthesized with Xilinx ISE 14.5. When synthesized with a better hardware efficiency for Xilinx Spartan 6 series field programmable gate array, the suggested architecture works at a frequency of 140.47 MHz.
Keywords: Image compression; Lifting, Pipeline, DWT, Filter Bank, Dual Scan.
Scope of the Article: Image Security