Simulation of Technical Indicators for Better Profits in the Indian Stock Market
Krishna Murthy Inumula1, Anupama Tadamarla2, K.Deeppa3
1Krishna Murthy Inumula, Associate Professor, Symbiosis Institute of International Business (SIIB), Symbiosis International University, Pune.
2Anupama Tadamarla, Faculty Member, IBS, `Pune and Research Scholar, Symbiosis International University, Pune.
3K.Deeppa, Faculty Member, IBS, Pune.
Manuscript received on 2 August 2019. | Revised Manuscript received on 8 August 2019. | Manuscript published on 30 September 2019. | PP: 1612-1619 | Volume-8 Issue-3 September 2019 | Retrieval Number: C4256098319/2019©BEIESP | DOI: 10.35940/ijrte.C4256.098319
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Interleaver is an indispensable component in the design of Turbo encoder and Turbo Decoder. QPP interleaver is a 3GPP specified conflict free interleaver for turbo channel coding scheme for all code block sizes of 40 to 6144. Thus the efficient design of a conflict free reconfigurable QPP interleaver for turbo encoder and turbo decoder is a pre-eminent task in turbo channel coding scheme. In this article, Design of a simplified reconfigurable (40 to 6144 block sizes) Recursive QPP interleaver for computation of address locations to minimize the computational complexity and to avoid storage of interleaver tables has been presented. The proposed interleaver will be further integrated in the design and implementation of high throughput parallel turbo decoder. The proposed design is synthesized and implemented using 28nm CMOS technology Zynq Zed FPGA and achieved low processing timing constraints, utilization and power constraints compared with other conventional designs.
Keywords: Interleaver, Memory contention, Turbo codes, QPP.
Scope of the Article: Computer Graphics, Simulation, and Modelling