Reliability Prediction for Low Power Adiabatic Logic Families
Suresh Kumar Pittala1, Swajeeth Pilot. Panchangam2, A. Jhansi Rani3
1Suresh Kumar Pittala, Associate Professor, Department of ECE, DVR & Dr. HS MIC College of Technology, Kanchikacherla (A.P), India.
2Swajeeth Pilot. Panchangam, M.S, Department of Reliability Engineering Centre, Indian Institute of Technology, Kharagpur (West Bengal), India.
3Dr. A. Jhansi Rani, Professor, Department of ECE, V.R. Siddhartha Engineering College, Vijayawada (A.P), India.
Manuscript received on 18 August 2012 | Revised Manuscript received on 25 August 2012 | Manuscript published on 30 August 2012 | PP: 116-121 | Volume-1 Issue-3, August 2012 | Retrieval Number: C0283071312/2012©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: This paper focuses on predicting reliability of low power adiabatic logic families. Reliability logic diagram for each logic family is briefly discussed. Power dissipation is an important aspect of digital computing systems because of the increasing demand for portable electrical digital systems. Unlike conventional CMOS logic circuits, adiabatic circuits recover and reuse circuit energy that would otherwise be dissipated as heat and thus improve the portability of system. Development of adiabatic logic as an approach to reduce the energy dissipation of the digital circuits has became a major focus of interest over the last one decade. In this paper, we performed simulations at the schematic level using a standard 0.18 µm CMOS technology. The performance and power dissipation of the logic styles are evaluated for a maximum frequency of operation of 100MHz.
Keywords: Reliability Prediction, Adiabatic System, Low Power Digital System, CMOS Logic Circuits, Power Dissipation.
Scope of the Article: Structural Reliability Analysis