Design and Implementation of DSSS-CDMA Transmitter and Receiver for Reconfigurable Links Using FPGA
R. Sarojini1, Ch.Rambabu2
1R. Sarojini, M. Tech. Student, Department of GEC, SR Gudlavalleru Engineering College, Gudlavalleru (A.P), India.
2Ch.Rambabu, Assistant professor, Department of GEC, SR Gudlavalleru Engineering College, Gudlavalleru (A.P), India.
Manuscript received on 18 August 2012 | Revised Manuscript received on 25 August 2012 | Manuscript published on 30 August 2012 | PP: 169-175 | Volume-1 Issue-3, August 2012 | Retrieval Number: C0274071312/2012©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Direct sequence spread Spectrum (DSSS), is also called as direct sequence code division multiplexing (DS-CDMA). In direct sequence spread spectrum, the stream of information to be transmitted is divided into small pieces, each of which is allocated across to a frequency channel across the spectrum. A data signal at the point of transmission is combined with a higher data-rate bit sequence (also called chipping code) that divides the data according to a spreading ratio. The redundant chipping code helps the signal resist interference and also enables the original data to be recovered if data bits are damaged during the transmission. Direct sequence contrasts with the other spread spectrum process, known as frequency hopping spread spectrum. Frequency hopping code division multiple access (FH-CDMA), in which a broad slice of the bandwidth spectrum is divided into many possible broadcast frequencies. In general, frequency-hopping devices use, less power and are cheaper, but the performance of DS-CDMA systems is usually better and more reliable. In this project direct sequence spread spectrum principle based code division multiple access (CDMA) transmitter and receiver is implemented in VHDL for FPGA. The transmitter module mainly consists of data generator, programmable chip sequence generator (PN sequence generator), direct digital frequency synthesizer (DDFS), BPSK modulator blocks. The receiver modular mainly consists of BPSK demodulator, programmable chip sequence generator (PN sequence generator), matched filters, threshold detector blocks. Modelsim 6.2(MXE) tool will be used for functional and logic verification at each block. The Xilinx synthesis technology (XST) of Xilinx ISE 9.2i tool will be used for synthesis of transmitter and receiver on FPGA Spartan 3E.
Keywords: CDMA, DSSS, BPSK, PN code, DDFS.
Scope of the Article: Mobile Adhoc Network