A Secure Architecture of Design for Testability Structures
K. Swaraja1, K. Meenakshi2, Padmavathi Kora3, Mamatha Samson4, G. Karuna5, A. Ushasree6
1K. Swaraja, ECE, GRIET, Hyderabad, India.
2K. Meenakshi, ECE, GRIET, Hyderabad, India.
3Padmavathi Kora, ECE, GRIET, Hyderabad, India.
4Mamatha Samson, ECE, GRIET, Hyderabad, India.
5G. Karuna, CSE, GRIET, Hyderabad, India.
6A. Ushasree, ECE, GRIET, Hyderabad, India.
Manuscript received on 16 March 2019 | Revised Manuscript received on 20 March 2019 | Manuscript published on 30 July 2019 | PP: 2816-2820 | Volume-8 Issue-2, July 2019 | Retrieval Number: B1884078219/19©BEIESP | DOI: 10.35940/ijrte.B18840.078219
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: The structures of Scan-based Design for Testability are extremely susceptible towards unapproved access of the signals present inside the chip. This paper suggests a protected output based plan which averts the unapproved access without any compromise in the testability. A unique key for each test vector is provided in the proposed secure architecture. These inimitable keys are produced by a multi-polynomial linear feedback shift register (LFSR) in addition they are utilized as test vectors. The dimensions of the multi polynomial LFSR bit is saved bigger than the dimension of key so as to augment the level of security to the key. As the keys are concealed within the test vectors, there is reduction in area overhead. The amount of security is improved predominantly by changing the key for all test vectors, along with the location of the bit in the test vector by choosing a valid combination out of available test vector generated by multi polynomial LFSR.
Index Terms: Design for Test (DFT), Scan Chain, Multi Polynomial LFSR, Testability, Security.
Scope of the Article: Block Chain-Enabled IoT Device and Data Security and Privacy