Energy Efficient Digital Circuits using Two Phase Clocking Sub-Threshold Adiabatic Logic
M. Bharathi1, N. Padmaja2, D. Leela Rani3
1N.Padmaja, Professor of ECE, Center for Communication and Signal Processing, Sree Vidyanikethan Engineering College, Tirupati.
2D.Leela Rani, Professor of ECE, Center for Communication and Signal Processing, Sree Vidyanikethan Engineering College, Tirupati.
3M.Bharathi, Assistant Professor of ECE, Center for VLSI & Embedded Systems, Sree Vidyanikethan Engineering College, Tirupati.
Manuscript received on 08 March 2019 | Revised Manuscript received on 17 March 2019 | Manuscript published on 30 July 2019 | PP: 101-106 | Volume-8 Issue-2, July 2019 | Retrieval Number: B1692078219/19©BEIESP | DOI: 10.35940/ijrte.B1692.078219
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Abstract: Power is a major constraint in Digital VLSI circuits, due to reduction in sizes of Metal Oxide Semiconductor (MOS) transistors are scaling down. Low-power technologies are used to diminish the power utilization be able to be classified as Sub-threshold CMOS and Adiabatic logic tachniques. In, Sub-threshold CMOS defines a system which reduces the power utilization to inferior than the threshold voltage of a MOS Device, where as Adiabatic logic circuit is a method which minimizes the energy usage through suppress the applied voltage to the resistance of a given VLSI design. This effort deals to offer a subthreshold adiabatic logic circuit of low power CMOS circuits that uses 2φ clocking subthreshold Adiabatic Logic. The digital circuits were designed in HSPICE using 0.18 μm CMOS standard process technology. It is evident from the results that the 2φ Clocking Subthreshold Adiabatic design is beneficial in major application where power starving is of major significance at the same time as in elevated its performance efficiency in DSP processor IC, System on chip, Network on chip and High speed digital ICs.
Index Terms: Subthreshold Adiabatic, Threshold Voltage, Two Phase Clocking, Energy Dissipation & HSPICE
Scope of the Article: Digital System and Logic Design