An Optimized Counter Design using T Flip-Flop in Quantum-Dot Cellular Automata Technology
Adepu Hariprasad1, Sumanth Kumar Chennupati2
1Adepu Hariprasad, Department of Electronics & Communication Engineering, Kamala Institute of Technology and Science, Huzurabad (Telangana), India.
2Sumanth Kumar Chennupati, Department of Electronics & Communication Engineering, GIT, GITAM Deemed to be University, Visakhapatnam (Andhra Pradesh), India.
Manuscript received on 16 October 2019 | Revised Manuscript received on 25 October 2019 | Manuscript Published on 02 November 2019 | PP: 2707-2716 | Volume-8 Issue-2S11 September 2019 | Retrieval Number: B13320982S1119/2019©BEIESP | DOI: 10.35940/ijrte.B1332.0982S1119
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Conventional CMOS technology have lot of limitations and serious challenges threat this technology when scaled to a nano-level. Several alternative technologies have been proposed as solutions to overcome limitations and challenges encountered by CMOS. Quantum dot-cellular automata (QCA) is an emerging nanotechnology for the development of logic circuits such as combinational and sequential circuits.QCA seems to be best alternative to the conventional complementary metal-oxide semiconductor (CMOS) technology.QCA is a new computing paradigm in nanotechnology that can implement digital circuits with outstanding features such as ultralow power consumption, faster switching speed and extremely density structure . In this paper , a novel area efficient and optimized QCA layout design of sequential circuit T flip flop is proposed by which the QCA layout area has reduced by 57% , cell count improved by 56% in comparison with the earlier best designs. The use of proposed T flip flop in designing sequential circuits like synchronous 2 bit up counter,3 bit up counter and 4 bit up counter has reduced the QCA layout area by 65%,64% and 68% respectively where as QCA cell count are reduced by 53%, 62% and 59%.. The sequential circuits flip flop and counters are designed using three input XOR gate and are implemented by QCA layout. The paper also present the use of proposed T flip flop designed with 3 input XOR gate in designing not only synchronous binary up counters but also in synchronous binary down counter provides a significant reduction in the hardware and complexity than the existing methods. These circuits are simulated using computer aided design tool QCA Designer 2.0.3, which is a design and simulation tool for quantum dot cellular automata. The aim is to maximize the circuit density and focus on a QCA layout that uses minimal number of cells.
Keywords: CMOS, Logic Gates, Latency, Nanotechnology, Quatnum-dot Cellular Automata (QCA), T flip Flop, Counters.
Scope of the Article: Low-power design