2-Bit CMOS Comparator by Hybridizing PTL and Pseudo Logic
Vandana Choudhary1, Rajesh Mehra2
1Vandana Choudhary, M.E Student, Department of ECE NITTTR, Chandigarh, India.
2Rajesh Mehra, Associate Professor, Department of ECE NITTTR, Chandigarh, India.
Manuscript received on 21 May 2013 | Revised Manuscript received on 28 May 2013 | Manuscript published on 30 May 2013 | PP: 29-32 | Volume-2 Issue-2, May 2013 | Retrieval Number: B0564052213/2013©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: In this paper an area and power efficient hybrid comparator is proposed by hybridizing PTL and Pseudo logic design. This hybrid comparator is proposed to improve area and power in 120 nm technology and compared with the previous work. To improve area and power minimum number of transistor logic is used in the proposed hybrid comparator. The proposed comparator has been designed and simulated using DSCH 3.1 and Microwind 3.1 on 120nm. Also the simulation of layout and parametric analysis has been done for the proposed comparator design. Power and current variation with respect to the supply voltage and temperature has been performed on BSIM-4 and LEVEL-3 on 120nm. Results show that area consumed by the proposed hybrid comparator is 40.99% on 120nm technology. At 1.2V input supply voltage the proposed adder has shown an improvement of 42.69% in power on BSIM-4 120nm technology
Keywords: Magnitude Comparator; Binary Comparator; High speed; Low Power; Hybrid PTL/PSEUDO NMOS logic
Scope of the Article: Digital System and Logic Design