Fully Parallel Architecture of QC-LDPC Decoder for IEEE 802.11n Application
Monica Kalbande1, Shweta Hajare2, Tejswini Panse3, Pravin Dakhole4
1Monica Kalbande, Electronics Engineering Department ,Yeshwantrao Chavan College of Engg, Nagpur, India.
2Shweta Hajare*, Electronics Engineering Department, Yeshwantrao Chavan college of Engg, Nagpur, India.
3Tejswini Panse, Electronics Engineering Department, Yeshwantrao Chavan college of Engg, Nagpur, India.
4Pravin Dakhole, Electronics Engineering Department, Yeshwantrao Chavan college of Engg, Nagpur, India.
Manuscript received on April 30, 2020. | Revised Manuscript received on May 21, 2020. | Manuscript published on May 30, 2020. | PP: 1726-1731 | Volume-9 Issue-1, May 2020. | Retrieval Number: A2314059120/2020©BEIESP | DOI: 10.35940/ijrte.A2314.059120
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: A Low density parity check (LDPC) code, have become most accepted error correction code for efficient and reliable communication due to a good performance. The VLSI implementation of LDPC decoder is a big challenge. Iterative message passing decoding algorithms propose excellent error correction performance but a large decoding complexity for different code lengths and code rates. The LDPC codes decoder also faced many difficulties such as small chip areas , reduced interconnect complexities, lower power dissipation. In this paper, the design of the of Quasi Cyclic(QC)LDPC decoder for the IEEE 802.11n standard with 1/2 code rate, 648coward length and sub-block size z =27 have been designed. Initially different iterative algorithms for LDPC decoding are discussed. The Fully parallel architecture of the LDPC decoder for IEEE 802.11n standard using Min Sum decoding algorithm (MSA)has been designed. Further, the design Quasi Cyclic(QC) LDPC decoder for IEEE 802.11n have been modified by using a Finite State Machine (FSM) to control the complete decoding process.
Keywords: IEEE 802.11n , LDPC decoder, Min Sum, Quasi Cyclic.
Scope of the Article: Parallel and Distributed Algorithms