Design of New Tester Circuit for Fault Detection
Tulasi Deepala1, Sarada Musala2, Ramakrishna Kommu3
1Tulasi Deepala, Department of Engineering and Communication Engineering, Vignan’s Foundation for Science, Technology & Research, Deemed to be University, Guntur, A.P, India.
2Sarada Musala, Department of Engineering and Communication Engineering, Vignan’s Foundation for Science, Technology & Research, Deemed to be University, Guntur, A.P, India.
3Ramakrishna Kommu, Department of Engineering and Communication Engineering, Vignan’s Foundation for Science, Technology & Research, Deemed to be University, Guntur, A.P, India.
Manuscript received on 08 April 2019 | Revised Manuscript received on 16 May 2019 | Manuscript published on 30 May 2019 | PP: 3372-3375 | Volume-8 Issue-1, May 2019 | Retrieval Number: A2210058119/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Fault detection plays an important role in detecting faults and helps to reduces the yield loss in manufacturing process of ICs. Due to the smaller size and process variations, IC chips become more sensitive. Thus there is thriving necessity for fault tolerance which can be obtained by an efficient fault detection concept. In this paper, new tester circuit is designed for fault detection using different tester circuits that are existed. This design has been simulated in 180nm, 65nm CMOS technology using cadence Virtuoso tool. By using transmission gates instead of pass transistors the modified circuit provides full swing voltage at output.
Index Terms: Fault Detection, Fault Diagnosis, Fault Isolation, Redundancy Allocation, Tester circuit.
Scope of the Article: Design and Diagnosis