Design and Analysis of Power Efficient 64-Bit ALCCU
Dharmavaram Asha Devi1, Muchukota Suresh Babu2
1Dharmavaram Asha Devi, Department of Electronics & Communication Engineering, Sreenidhi Institute of Science and Technology, Hyderabad, India.
2Muchukota Suresh Babu, Department of Electronics & Communication Engineering, Sreenidhi Institute of Science and Technology, Hyderabad, India.
Manuscript received on 02 March 2019 | Revised Manuscript received on 10 March 2019 | Manuscript published on 30 July 2019 | PP: 162-166 | Volume-8 Issue-2, July 2019 | Retrieval Number: A1993058119/19©BEIESP | DOI: 10.35940/ijrte.A1993.078219
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Speed of any system depends on mainly two factors known as frequency and parllel processing. Such high speed processing systems are required in real time embedded systems. The existed systems are operated with maximum of 2 to 3 GHz. The proposed 64-bit ALCCU is a high-speed processing system that will perform arithmetic, logical and code conversion operations. It is implemented in structural style with Verilog Hardware Description Language. This design is a high speed, low powered and will perform 32 operations. Its data size is 64_bit, implemented on xc7a100tcsg324-1 which is an Artix 7, 100K gate technology FPGA with a CSG 324 package. Satisfactory low power (less than 1W) has been observed with varying clock rates of ranging from 10 MHz to 20 GHz. The analysis is done with Low Voltage CMOS I/O standards from 1.2 to 3.3V range. The application of the proposed design can be used as an IP in high speed processors and controllers.
Index Terms: Arithmetical, Logical and Code-Conversion Unit (ALCCU), Field Programmable Gate Array, Hardware Description Language, Low Voltage CMOS.
Scope of the Article: Natural Language Processing