Analysis of Various TSPC Based D Flip Flops
Anwesha Deb1, Shobha Sharma2, Amita Dev3
1Anwesha Deb, Department of Electronics and Communication Engineering, Indira Gandhi Delhi Technical University for Women, Delhi, India.
2Shobha Sharma, (Corresponding Author) Assistant Professor, Department of Electronics and Communication Engineering, Indira Gandhi Delhi Technical University for Women, Delhi, India.
3Amita Dev, Pro Vice Chancellor, Indira Gandhi Delhi Technical University for Women, Delhi, India.
Manuscript received on 13 April 2019 | Revised Manuscript received on 19 May 2019 | Manuscript published on 30 May 2019 | PP: 1716-1718 | Volume-8 Issue-1, May 2019 | Retrieval Number: A1382058119/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: The world is growing at an ultra-fast speed and so is the technology. Today small devices with maximum efficiency and minimum power are in demand and so came the flip flops. They are used in large number of applications ranging from data storage to microprocessors. In this paper, reviews of different models of D flip flop are presented including respective circuits and their description and working. They are based upon the TSPC logic which allows to represent the design of D flip flop with smaller area and lower power consumption as compared to master-slave configuration-based D flip flop.
Index Terms: AVL Technique, D Flip Flop, MTCMOS Technique, TSPC Logic.
Scope of the Article: Image Analysis and Processing