Analysis of Various Master-Slave Configuration based D Flip-Flops
Shivali1, Shobha Sharma2, Amita Dev3
1Shivali, Department of Electronics & Communication Engineering, Indira Gandhi Delhi Technical University for Women, Delhi, India.
2Shobha Sharma, (Corresponding Author) Assistant Professor, Department of Electronics & Communication Engineering, Indira Gandhi Delhi Technical University for Women, Delhi, India.
3Amita Dev, Pro Vice Chancellor, Indira Gandhi Delhi Technical University for Women, Delhi, India.
Manuscript received on 12 April 2019 | Revised Manuscript received on 17 May 2019 | Manuscript published on 30 May 2019 | PP: 1713-1715 | Volume-8 Issue-1, May 2019 | Retrieval Number: A1381058119/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: The needs of fast devices are growing day-by-day and so flip flops are coming into picture. For many digital devices flip flops are the elementary unit for construction. They are termed as one bit memory element. This paper enumerates review on various earlier proposed master slave configuration-based D flip flop models including respective circuits and their description. It includes NAND logic gate-based D flip flop, NOR logic gate-based D flip flop, 2×1 mux-based D flip flop including MTCMOS technique and transmission gate-based D flip flop. All these topologies are used to develop D latch which are then converted into D flip flop by the cascading of two D latches in master-slave configuration.
Index Terms: D Flipflop, Gates, Master-Slave Configuration, Multiplexer
Scope of the Article: Analysis of Algorithms and Computational Complexity