Design and Implementation of Energy Efficient SAR Analog to Digital Converter
B. Satish1, Prabhu G Benakop2
1B. Satish, Research Scholar, JNTUH, Hyderabad, India
2Prabhu G Benakop, Principal, Indur Institute of Engineering and Technology, Hyderabad, India
Manuscript received on 06 April 2019 | Revised Manuscript received on 12 May 2019 | Manuscript published on 30 May 2019 | PP: 974-977 | Volume-8 Issue-1, May 2019 | Retrieval Number: A1231058119/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: An energy efficient Successive Approximate Register Analog to Digital Converter (SAR ADC) is designed and implemented to meet the low power sensor applications using split capacitor Digital to Analog Converter (DAC). The split capacitor array DAC reduces the practical value of MSB Capacitor to 50%. The body bias based Dynamic Comparator is proposed for the SAR ADC to improve the linearity of ADC and to reduce the energy. The gate and Transistor level optimization is carried out using mixed logic technique for the reduction of transistors count in the digital SAR control logic block. Due to the split capacitor DAC, body biased comparator and mixed digital logic, the overall area and energy are reduced than the existing SAR ADC architectures.
Index Terms: ADC, Low Power, Dynamic Comparator, DAC and Transmission Gate Logic (TGL).
Scope of the Article: Energy Efficient Building Technology