Low Power High Speed Arithmetic Circuits
Kiran Kumar V G1, C Shantharama Rai2
1Kiran Kumar V G, Department of Electronics and Communication Engineering, A.J Institute of Engineering and Technology, Kottara, Mangalore, Karnataka India.
2Shantharama Rai C, Principal, AJ Institute of Engineering, Kottara, Mangalore, India.
Manuscript received on 16 March 2019 | Revised Manuscript received on 21 March 2019 | Manuscript published on 30 July 2019 | PP: 807-813 | Volume-8 Issue-2, July 2019 | Retrieval Number: A1064058119/19©BEIESP | DOI: 10.35940/ijrte.B1064.078219
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: In the Design of arithmetic circuits reducing area, high speed and power are the major areas in VLSI system design. In this paper parallel prefix adders like Kogge-stone adder, Breunt-Kung adder, Ladner-Fischer adder is designed .Radix-4 Booth multiplier is designed by using Kogge-Stone adder. 16 bit Vedic multiplier is done by using Urdhwa Triyambaka sutra .8bit Vedic division is implemented by using Crumbs method so as to reduce the area, LUT tables and increase the speed as well as to reduce the Power dissipiation. The design is synthesized using Xilinx ISE 14.1 design suite.
Index Terms: Kogge-Stone Adder, Breunt-Kung Adder, Ladner-Fischer Adder .Radix-4 Booth Multiplier.
Scope of the Article: Nanometer-Scale Integrated Circuits