Implementation of High Speed Low Power Systolic Multiplier Based on Irreducible Trinomials
G.Erna1, S.Tamilselvan2
1G. Erna, Research Scholar, Department of ECE, Pondicherry Engineering College, Puducherry, India.
2S.Tamilselvan, Associate Professor, Department of ECE, Pondicherry Engineering College, Puducherry, India.
Manuscript received on January 02, 2020. | Revised Manuscript received on January 15, 2020. | Manuscript published on January 30, 2020. | PP: 223-225 | Volume-8 Issue-5, January 2020. | Retrieval Number: D6799118419/2020©BEIESP | DOI: 10.35940/ijrte.A1020.018520
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: This paper presents a high speed low power systolic multiplier based on irreducible trinomials which is implemented using GF (2M). To calculate a set of d partial products in each Handling Element (HE) during every cycle we suggest multiplication algorithm of digit level. By using the systolic channels independently, operands in the proposed structure will be reduced and accumulated by partial products. Functional verification (Simulation) of the multiplier is done by using Xilinx ISE and synthesis is done by using Xilinx XST. The synthesized design is implemented on Zynq7000 FPGA. After completion of the synthesis, it is found that the proposed multiplier achieved power consumption of 2.9mW. Area and the performance of the multiplier is optimized in the proposed structures.
Keywords: Digit-Level Multiplication, Handling Elements, Irreducible Trinomials, Systolic Multiplier.
Scope of the Article: Digital System and Logic Design.