Design of Low Power Sram Memory Using 8t Sram Cell
Nahid Rahman1, B. P. Singh2
1Nahid Rahman, Department of Electronics and Communication, FETMITS (Deemed university), Lakshmangarh (Rajasthan), India.
2B. P. Singh, Department of Electronics and Communication, FETMITS (Deemed university), Lakshmangarh (Rajasthan), India.
Manuscript received on 21 March 2013 | Revised Manuscript received on 28 March 2013 | Manuscript published on 30 March 2013 | PP: 123-127 | Volume-2 Issue-1, March 2013 | Retrieval Number: A0526032113/2013©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Low power design has become the major challenge of present chip designs as leakage power has been rising with scaling of technologies. As modern technology is spreading fast, it is very important to design low power, high performance, and fast responding SRAM (Static Random Access Memory) since they are critical component in high performance processors. The Conventional 6T SRAM cell is very much prone to noise during read operation. To overcome the problems in 6T SRAM cell, researchers have proposed different SRAM topologies such as 8T, 9T, 10T etc. bitcell design. These designs can improve the cell stability but suffer from bitline leakage noise. In this paper, an SRAM memory has been designed to overcome power consumption problem. It also improves the Cell stability by increasing the Read Static-Noise-Margin.
Keywords: CMOS logic, SRAM, VLSI, Read-Static Noise Margin (SNM), Stability and Power Consumption.
Scope of the Article: Low-power design