A Novel Architecture for Super Speed Data Communication for USB 3.0 Device Using FPGA
Amit Kumar Amod1, Ansuman Dipti Sankar Das2, Tapas Sahu3, Sekhar Sahani4, Deepak Kumar Panda5
1Amit Kumar Amod, Department of ECE, NIT Rourkela (Odisha), India
2Ansuman Dipti Sankar Das, Department of ECE, NIT Rourkela (Odisha), India.
3Tapas Sahu, Department of Electronics, KIIT University, Bhubaneswar (Odisha), India.
4Sekhar Sahani, Department of Electronics, KIIT University, Bhubaneswar (Odisha), India.
5Deepak Kumar Panda, Department of Electronics, KIIT University, Bhubaneswar (Odisha), India.
Manuscript received on 21 March 2013 | Revised Manuscript received on 28 March 2013 | Manuscript published on 30 March 2013 | PP: 83-87 | Volume-2 Issue-1, March 2013 | Retrieval Number: A0515032113/2013©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: The need for SuperSpeed data communication leads to the use of USB 3.0. USB 3.0 utilizes dual bus architecture which provides both SuperSpeed and non Super Speed connectivity. This can be possible by mixing the advantage of parallel and serial data transfer. This paper provides a novel architecture for communication between USB 3.0 device and USB 3.0 host controller at a data rate of maximum up to 5.0 Gbps using Altera’s Stratix IV FPGA. To maintain synchronization between GPIF II and PCIe hard IP, FIFO is used. PLL is used to provide clock signal at different frequencies.
Keywords: FIFO, FPGA, GPIF, Hard IP, PLL, USB 3.0.
Scope of the Article: Optical and High-Speed Access Networks