Design and FPGA Implementation of a Lifting Scheme 2D DWT Architecture
Naseer M. Basheer1, Mustafa Mushtak Mohammed2
1Mr. Mustafa Mushtak Mohammed, Department of Computer Engineering, Technical College, Mosul, Iraq.
2Dr. Naseer M. Basheer, Department of Computer Engineering, Technical College, Mosul, Iraq.
Manuscript received on 21 March 2013 | Revised Manuscript received on 28 March 2013 | Manuscript published on 30 March 2013 | PP: 34-38 | Volume-2 Issue-1, March 2013 | Retrieval Number: A0473032113/2013©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: This paper presents an area efficient, and simple design, of multilevel two dimensional discrete wavelet transform (2-D DWT) modules for image compression. The proposed architecture is based on lifting scheme approach, using the (5/3) wavelet filter, aiming to reduce the hardware complexity and size of the on-chip memory. This architecture consists of a control unit, a processor unit, two on-chip internal memories to speed up system operations, and an on-board off-chip external memory (Intel strata parallel NOR flash PROM). The 2-dimensinal discrete wavelet transform lifting scheme algorithm has been implemented using MATLAB program for both modules forward discrete wavelet transform (FDWT) and inverse discrete wavelet transform (IDWT) to determine suitable word length for DWT coefficients and the peak signal to noise ratio (PSNR) for the retrieved image. The decomposition algorithm of this transform is designed and synthesized with the VHDL language and then implemented on the FPGA Spartan 3E starter kit (XC3S500E) to check validation of results and performance of design.
Keywords: Two Dimensional Discrete Wavelet Transform (2-D DWT), Lifting Scheme, (5/3) Wavelet Filter, and FPGA Applications.
Scope of the Article: Innovative Mobile Applications