Data Encoding Techniques to Reduce the Switching Activity and Crosstalk Delay of on-Chip Data Interconnects
M. Chennakesavulu1, T. Jayachandra Prasad2, V. Sumalatha3
1M. Chennakesavulu, Research Scholar, Department of Electronics and Communication Engineering, JNTUA College of Engineering, Ananthapuramu, Working RGMCET, (Andhra Pradesh), India.
2T. Jayachandra Prasad, Professor, Department of Electronics and Communication Engineering, RGM College of Engineering & Technology, Nandayal (Andhra Pradesh), India.
3V. Sumalatha, Professor, Department of Electronics and Communication Engineering, JNTUA College of Engineering, Ananthapuramu, (Andhra Pradesh), India.
Manuscript received on 26 February 2019 | Revised Manuscript received on 13 March 2019 | Manuscript Published on 17 March 2019 | PP: 59-64 | Volume-7 Issue-ICETESM18, March 2019 | Retrieval Number: ICETESM15|19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: System on Chip (SoC) is providing not only many opportunities but also many challenges. Scaling has applied in SoC to accommodate many processing elements in single silicon area. Scaling has provided decrement in gate delay and the increment in interconnect delay. Coupling capacitance has formed when the spacing between the adjacent interconnects has decreased and it becomes dominant factor when the spacing between the adjacent interconnects has further decreased. Coupling capacitance caused to increment in coupling switching transitions and crosstalk. Coupling switching activity directly affects the dynamic power and crosstalk affects the reliability and performance. Coupling switching activity and crosstalk depend on data patterns travelled on interconnects. Hence, data encoding techniques are essential to alter the data, such way that to reduce the coupling switching activity and crosstalk. In this paper, three data encoding techniques are proposed to limit the switching activity and crosstalk delay in five-wire model. Performance of proposed data encoding techniques has compared to existing techniques. Moreover, efficiency of data encoding techniques is analyzed in terms self -switching activity, coupling switching activity, energy consumption, and crosstalk delay classes for 8-bit data.
Keywords: Crosstalk Delay, Data Encoding Techniques, Switching Activity, System on Chip (SoC).
Scope of the Article: Routing, Switching and Addressing Techniques