An Efficient High Speed GDI Dadda Multiplier
Y E Vasanth Kumar1, G Rupa Devi2, B Srinivasu3, B Niharikha4, Ch Sunil Raju5
1Y.E. Vasanth Kumar, Department of Engineering and Communication Engineering, Raghu Engineering College Autonomous, Visakhapatnam, India.
2G. Rupa Devi, Department of Engineering and Communication Engineering, Raghu Engineering College Autonomous, Visakhapatnam, India.
3B. Srinivasu, Department of Engineering and Communication Engineering, Raghu Engineering College Autonomous, Visakhapatnam, India.
4B. Niharikha, Department of Engineering and Communication Engineering, Raghu Engineering College Autonomous, Visakhapatnam, India.
5Ch. Sunil Raju, Department of Engineering and Communication Engineering, Raghu Engineering College Autonomous, Visakhapatnam, India.
Manuscript received on 15 April 2019 | Revised Manuscript received on 21 May 2019 | Manuscript published on 30 May 2019 | PP: 672-675 | Volume-8 Issue-1, May 2019 | Retrieval Number: F2808037619/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: In digital processing low-energy multipliers are our prime concern. We present energy minimization technique in this paper. To sieve out the futile switching power different approaches are exploited such as CMOS, PTL and GDI. In finite impulse response, convolution and other DSP applications multiplication occurs frequently. A good multiplier should provide good speed, low power and compact in a VLSI design. We propose a low PDP multiplier exploiting Dadda algorithm. Based on the proposed design PTL and GDI Dadda multipliers are designed and compared with conventional Dadda Multiplier. Tanner EDA has been used for design validation.
Index Terms: CMOS, Dadda Multiplier, GDI, PTL.
Scope of the Article: Energy Efficient Building Technology