A Novel Two-Fold Edge Activated Memory Cell with Low Power Dissipation and High Speed
K Mariya Priyadarshini1, R. S. Ernest Ravindran2
1K Mariya Priyadarshini, Department of Engineering and Communication Engineering, KLEF Deemed to be University, Green Fields, Vaddeswaram, Guntur, Andhra Pradesh
2Dr. R. S. Ernest Ravindran, Department of Engineering and Communication Engineering, KLEF Deemed to be University, Green Fields, Vaddeswaram, Guntur, Andhra Pradesh
Manuscript received on 07 April 2019 | Revised Manuscript received on 11 May 2019 | Manuscript published on 30 May 2019 | PP: 1491-1495 | Volume-8 Issue-1, May 2019 | Retrieval Number: F2449037619/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: In today’s increasing demand of higher integration levels in VLSI and ULSI circuits’ memory capacity and frequency of RAM is playing a major role in designing. Flip-flops are the micro cells for memories to store binary values. D flip-flops now days are used instead of any other because its designing is easy as far as area and power constraints are considered. So as to increase the bit rate of Flip-flop many triggering techniques were propose like single edge triggering and dual edge triggering. A novel D Flip-flop which uses only 14 transistors is explained using Two Fold Edge Triggering in this paper. From this paper we come to an understanding that at any temperature or at any supply voltage levels the proposed Flip-flop is efficient. Even though Power Delay product increases at lower voltage levels but still it is less compared to existing method. The input to output delay is greatly decreased as the number of transistors is reduced in dual data paths.
Keywords: Memory Cell, Clock Efficiency, Signal Feed-Back, Mentor Graphics.
Scope of the Article: Low-power design