Network on Chip: A Survey on Router Design and Algorithms
Krutthika H.K1, Rajashekara2
1Krutthika H K Department, of Electronics and Communication, Dayananda Sagar College of Engineering, Bengaluru, (Karnataka), India
2Dr. Rajashekara, Ph.D(IITB) Department, of Electronics and Communication, Philips India Limited, Bengaluru, (Karnataka), India
Manuscript received on 23 March 2019 | Revised Manuscript received on 30 March 2019 | Manuscript published on 30 March 2019 | PP: 1687-1691 | Volume-7 Issue-6, March 2019 | Retrieval Number: F2131037619/19©BEIESP | DOI: 10.35940/ijrte.F2131.037619
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: The increase in the applications for the innovative technologies has further increased the computing resources in a single chip. In such scenario, different application desires computing resources to build on a Single Chip. Therefore, interconnection between the IP cores becomes another challenging task. So, this led to the innovation of the Network on Chip as a novel platform those networks inside the System on Chip. There are many disadvantages of the traditional bus based architectures, as it blocks the traffic. The network topologies, routing algorithms and router architectures are the utmost critical part of any network structure. The execution of the system is measured by throughput. The throughput and effectiveness of interconnect depends on the system parameters. In this paper, we are reviewing the previous methods and approaches of routing algorithms and router architectures of NoC.
Keywords: Network on Chip (NoC), System on Chip (SoC), Routing, Intellectual Property (IP), Network Interface (NI)
Scope of the Article: Computer Network