Code Acquisition and Tracking of IRNSS Signals
Anirudh Lanka1, Aishwarya Shivani R.2, Amoolya R. Bayari3, Suresh Dakkumalla4, Shylashree N.5
1Anirudh Lanka, Department of Electronics and Communication, Rashtreeya Vidyalaya College of Engineering, Bangalore (Karnataka), India.
2Aishwarya Shivani R., Department of Electronics and Communication, Rashtreeya Vidyalaya College of Engineering, Bangalore (Karnataka), India.
3Amoolya R. Bayari, Department of Electronics and Communication, Rashtreeya Vidyalaya College of Engineering, Bangalore (Karnataka), India.
4Suresh Dakkumalla, ISTRAC, ISRO, Peenya, Bangalore (Karnataka), India.
5Shylashree N., Department of Electronics and Communication, Rashtreeya Vidyalaya College of Engineering, Bangalore (Karnataka), India.
Manuscript received on 28 April 2019 | Revised Manuscript received on 10 May 2019 | Manuscript Published on 17 May 2019 | PP: 629-635 | Volume-7 Issue-6S4 April 2019 | Retrieval Number: F11290476S419/2019©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Navigation using the Indian Regional Navigation Satellite System (IRNSS) requires processing of the lowest raw data received from the corresponding satellites. The acquired Radio Frequency signal is subjected to a software based IRNSS receiver consisting of a Numerically Controlled Oscillator to convert from Radio Frequency Range to Intermediate Frequency Range for further processing. The converted signal is then subjected to various algorithms for achieving Code Acquisition, Locking and Tracking to complete the navigation. This paperdiscussesabout building a software based IRNSS receiver to simulate the navigation behavior in real time. All the simulation codes are written in VHDL and in accordance with the Zynq-706 FPGA board.The simulation manifests that Serial Acquisition consumes the lowest resource, but is time exhausting with 41933 iterations. Whereas the PCPS technique requires only 41 (or 1023 for PFSS) iterations but uses higher order DSP processors.
Keywords: Code Acquisition, Code Tracking, Carrier Tracking, Parallel Frequency Space Search, Parallel Code Phase Search, Phase Locked Loop, Delay Locked Loop, Frequency Locked Loop.
Scope of the Article: Signal Control System & Processing