Design and Implementation of Sequential Circuit Based on Low Power Using 45nm Technology
S. Mohamedsulaiman1, B. Jaison2, M. Anto Bennet3, Yacooprahman. S4, Shanmugapriyan V5, Albert Santhosh Raj. j6, Sathishkumar. V7
1Mohamed Sulaiman, Assistant Professor, Department of Electronics & Communication Engineering, Vel Tech, Chennai (Tamil Nadu), India.
2Jaison, Associate Professor, Department of CSE, RMK Engineering College, (Tamil Nadu), India.
3Anto Bennet, Professor, Department of Electronics & Communication Engineering, Vel Tech, Chennai (Tamil Nadu), India.
4Yacoop Rahman. S, UG Student, Department of Electronics and Communication Engineering, Vel Tech, Chennai (Tamil Nadu), India.
5Shanmuga Priyan V, UG Student, Department of Electronics and Communication Engineering, Vel Tech, Chennai (Tamil Nadu), India.
6Albert Santhosh Raj J, UG Student, Department of Electronics and Communication, Vel Tech, Chennai (Tamil Nadu), India.
7Sathish Kumar. V, UG Student, Department of Electronics and Communication Engineering, Vel Tech, Chennai (Tamil Nadu), India.
Manuscript received on 24 April 2019 | Revised Manuscript received on 03 May 2019 | Manuscript Published on 07 May 2019 | PP: 212-217 | Volume-7 Issue-6S3 April 2019 | Retrieval Number: F1043376S19/2019©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: A low power voltage CMOS frequency divider using power gating technique, that’s why it reduces the overall power consumption of circuit and increases the efficiency of circuit. .A memory element consumes 70 percent of total power in an integrated circuit. As flip-flops are the main area of memory elements used on any portable device, the major concern to reduce flip-flop energy consumption will help reduce power consumption in an I In we designed a flip-flop using CMOS logic; it consumes less energy than conventional gates designed. Transistors switching occurs when input and clock is applied. proposed clocked D flip-flop is used in frequency divider circuit .The frequency divider is design by use the technique of low power CMOS designs. Here number of transistor is reduced in proposed and demonstrate various parameters and shows reduced leakage power , Delay andnoise margin of the circuit to analyze its performance in 45nm technology with power gating and pass transistor technology. The simulation results were done with cadence tool virtuoso environment at room temperature 27ºC with various supply voltage ranges (0.7 to 1.2 V).
Keywords: Frequency Divider, Set Value, XOR Gate, T Flip Fop, Leakage Power, Area, Delay, 45nm Technology, Cadence.
Scope of the Article: Low-power design