Design of Vedic Multiplier using GDI Method
P. Manju1, P. B. Sreelakshmi2, T. Madhavi3
1P. Manju, Assistant Professor, Department of Electronics & Communication Engineering, Malla Reddy Engineering College for Women, (Telangana), India.
2P. B. Sreelakshmi, M.Tech, Department of Electronics & Communication Engineering, GITAM University, Visakhapatnam (Andhra Pradesh), India.
3Dr. T. Madhavi, Professor, Department of Electronics & Communication Engineering, GITAM University, Visakhapatnam (Andhra Pradesh), India.
Manuscript received on 24 April 2019 | Revised Manuscript received on 06 May 2019 | Manuscript Published on 17 May 2019 | PP: 227-229 | Volume-7 Issue-6S4 April 2019 | Retrieval Number: F10420476S419/2019©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Multipliers are the main building blocks for many of the fast processing systems [1]. The need for high speed multipliers increases as the need for high speed processors increases. Many multipliers have been developed to enhance the performances of the circuit. Among them Vedic multipliers are the rapid and powerless multipliers. Vedic multipliers are supported by Vedic mathematics and it consists of sixteen sutras or algorithms to perform logical operations. This paper focuses on designing Vedic multiplier using novel adder based on vertically and crosswise method of Vedic mathematics, which uses GDI technology and further it is compared with existing CMOS technology. Vedic multipliers are designed with 250nm technology and approved using Tannerv15.2. Simulated result proves that the Vedic multiplier using novel adder is more efficient.
Keywords: Back end Tools, CMOS, Delay, GDI (Gate Diffusion Input), Logic Family, Vedic Multiplier.
Scope of the Article: Microstrip Antenna Design and Application