Design and Analysis of High Performance Double Edge Triggered D-Flip Flop
Ravi.T1, Irudaya Praveen.D2, Kannan.V3
1Ravi.T, Research Scholar, Sathyabama University, Chennai (Tamil Nadu), India.
2Irudaya Praveen.D, M. Tech. Student, Department of VLSI Design, Sathyabama University, Chennai (Tamil Nadu), India.
3Kannan.V, Principal, Jeppiaar Institute of Technology, Kunnam (Tamil Nadu), India.
Manuscript received on 21 January 2013 | Revised Manuscript received on 28 January 2013 | Manuscript published on 30 January 2013 | PP: 139-142 | Volume-1 Issue-6, January 2013 | Retrieval Number: F0445021613/2013©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: The power consumption of a system is a crucial parameter in modern VLSI circuits especially for low power applications. This paper proposed a new Double Edge Triggered D-Flip Flop (DETFF) which is suitable for low power applications. The proposed DETFF is having less number of clocked transistors than existing designs. The proposed DETFF is simulated with different clock frequencies ranging from 1MHz to 2GHz. Simulation results show lowest average power and least delay than existing designs. Further, the average power and the PDP are improved by 77.23% and 89.11% when compared with existing design respectively, which claims that proposed design is suitable for low power and high performance applications.
Keywords: DETFF, Power, Delay, PDP
Scope of the Article: High Performance Computing