A Low Voltage High Speed Segmented Current Steering DAC for Neural Stimulation Application
Jayeshkumar J. Patel1, Amisha P. Naik2
1Prof. Jayeshkumar J. Patel, Research Scholar, Institute of Technology, Nirma University, Ahmedabad, India.
2Dr. Amisha P. Naik, Associate Professor, Institute of Technology, Nirma University, Ahmedabad, India.
Manuscript received on January 05, 2020. | Revised Manuscript received on January 25, 2020. | Manuscript published on January 30, 2020. | PP: 4270-4274 | Volume-8 Issue-5, January 2020. | Retrieval Number: E6586018520/2020©BEIESP | DOI: 10.35940/ijrte.E6586.018520
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: A multi-phasic neural stimulator using current steering Digital to Analog Converter with low resolution is in great demand to ameliorate symptoms of Parkinson’s disease and disorders of consciousness. This article presents 5-bit segmented DAC designed for such applications. In order to simulate the design, cadence virtuoso tool with 180 nm MOS technology is used. The results obtained after simulation indicate that the proposed DAC offers +0.34 LSB INL and +0.36 LSB value for DNL. For the input of 200 MSPS, the power dissipation is about 22 mW when working with 1.8 V of supply voltage.
Keywords: Component; DAC, DNL, INL, Digital-To-Analog Converter, CMOS Current-Steering DAC, SFDR.
Scope of the Article: Seismic Evaluation of Building Nonstructural Components.