Design of 1-V, 12-Bit Low Power Incremental Delta Sigma ADC for CMOS Image Sensor Applications
D. S. Shylu Sam1, S. Radha2, D. Jackuline Moni3, P. Sam Paul4, J. Jecintha5
1D. S. Shylu, Associate Professor, Department of ECE, Karunya Institute of Technology and Sciences, Coimbatore (Tamil Nadu), India.
2S. Radha, Assistant Professor, Department of ECE, Karunya University, Coimbatore (Tamil Nadu), India.
3Dr. D. Jackuline Moni, Professor, Department of ECE, Karunya Institute of Technology and Sciences, Coimbatore (Tamil Nadu), India.
4P. Sam Paul, Professor, Department of Mechanical Engineering, Karunya Deemed University, Coimbatore (Tamil Nadu), India.
5J. Jecinth, M.Tech, Karunya, Deemed University, Coimbatore (Tamil Nadu), India.
Manuscript received on 23 April 2019 | Revised Manuscript received on 02 May 2019 | Manuscript Published on 08 May 2019 | PP: 249-254 | Volume-7 Issue-5S3 February 2019 | Retrieval Number: E11470275S19/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: This work describes a 12-bit low power incremental delta sigma analog to digital converter (ADC) suitable for CMOS image sensor applications. The resolution of the delta sigma ADC is improved by sharing an op-amp between two stages of the modulators. Op-amp is the main building block of delta sigma ADC and the power consumption is reduced by self-biasing amplifier. The prime conversion is done by using comparator. The 12-bit incremental delta sigma ADC is designed in 90nm CMOS process. Simulation result shows that the power consumption for 12-bit incremental delta sigma ADC is 0.001mW.
Keywords: Delta-Sigma ADC, Op-amp Sharing, Self-biased Amplifier, Low Power, Comparator.
Scope of the Article: Low-power design