Reduction of Power in Sram Cell with Gated VDD Methodology
Aswini Valluri1, Muralidharan Jayabalan2
1Aswini Valluri, Ph.D Research Scholar, Department of Electronics and Communication Engineering, VFSTR Deemed to be University, Vadlamudi (A.P), India.
2Dr. Muralidharan Jayabalan, Associate Professor, Department of Electronics and Communication Engineering, VFSTR Deemed to be University, Vadlamudi (A.P), India.
Manuscript received on 14 February 2019 | Revised Manuscript received on 05 March 2019 | Manuscript Published on 08 June 2019 | PP: 380-382 | Volume-7 Issue-5S4, February 2019 | Retrieval Number: E10800275S419/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Memories are the most important part of portable battery operated digital devices. Since the standard SRAM cells are much power hungry, therefore reducing the power dissipation of memory plays an important role in improving the performance of the system. A low power Static RAM Cell design is analyzed by employing Gated Vdd technique. The outcomes are correlated with the standard 6T, 7T Static RAM cells which show that Gated Vdd technique yields better than the standard 6T and 7T Static RAM cells. The proposed cell dissipates 44.6% lesser power compared to the standard 6T Static RAM cell and 31.09% lesser power to the 7T Static RAM cell. Simulations are performed using Cadence Virtuoso tool with 180nm technology.
Keywords: SRAM (Static Random Access Memory), Power Dissipation, Gated Vdd, 180 Nm.
Scope of the Article: Low-power design